Lynne Jolitz term memory patent
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Lynne Jolitz Receives Term Memory Patent

Video - Do Patents Matter? Lynne Jolitz, has received a granted patent Term Addressable Memory of an Accelerator System and Method.

The patent addresses an improved term addressable memory and includes a mechanism for performing predetermined plurality of pattern matches of packets to classify them for use with stateful protocol processing units that can resolve session data spread across multiple data packets and process them for the ultimate destination. In a term addressable memory, redundant terms are recorded with a single memory entry. Two classes of terms are used to match packet addresses and application ports, as well as a much smaller session CAM that matches the aggregate match of all terms to a specific session.

The invention replaces a conventional content addressable memory such as that used in the "TCP/IP Network Accelerator System and Method" invented by Jolitz, Lawson, and Jolitz for InterProphet Corporation , a funded semiconductor company founded by William and Lynne Jolitz which pioneered and holds the fundamantal technology patents on Layer-4 low-latency protocol processing using dataflow design. InterProphet produced the most efficient and scalable TCP/IP hardware network server and storage card ever invented using SiliconTCP, as part of products such as EtherSAN.

Thrill of Parchment

Lynne was thrilled to receive the parchment for the patent from the US Patent Office. "There's nothing like the thrill of holding your own parchment with the gold seal and red ribbon with your own name on it. It has been worthwhile waiting for this for over three long years". The patent filing was in January of 2001, and like other semiconductor patents endured extensive review. Unlike most patents, Lynne's latest patent is unshared by other inventors or companies. News Quanta August 2004.

Related

US6768992: Term Addressable Memory of an Accelerator System and Method. Grant Date: July 27, 2004. Lynne G. Jolitz. An improved term addressable memory of an accelerator system and method includes a mechanism for performing predetermined plurality of pattern matches of packets to classify them for use with stateful protocol processing units that can resolve session data spread across multiple data packets and process them for the ultimate destination. The invention replaces a conventional content addressable memory (CAM) with a term addressable memory, whereby redundant terms are recorded with a single memory entry. Two classes of terms are recorded with a single memory entry. Two classes of terms are used to match packet addresses and application ports, as well as a much smaller session CAM that matches the aggregate match of all terms to a specific session. Filed Jan. 8, 2001 . See Lynne Jolitz term memory patent and TCP/IP network accelerator system and method which identifies classes of packet traffic for predictable protocols.

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