US6952409: Accelerator system and method. Issue Date: Oct 10, 2005. Lynne G. Jolitz. In a system consisting of a cell phone, wireless network, and a base station, for cell communication packets having a formatted header containing information about the packet, said cell phone comprising a modulator/RF detector and a DSP, the improvement comprising means for transparent bi-directional translation of audio/video protocols into Internet standard protocols, thereby allowing directed attachment to other stream oriented protocol devices without interposed protocol translation while reducing complexity. Filed Jan. 8, 2001 . See also Lynne Jolitz term memory patent and TCP/IP network accelerator system and method which identifies classes of packet traffic for predictable protocols and Term Addressable Memory of an Accelerator System and Method.
US6768992: Term Addressable Memory of an Accelerator System and Method. Grant Date: July 27, 2004. Lynne G. Jolitz. An improved term addressable memory of an accelerator system and method includes a mechanism for performing predetermined plurality of pattern matches of packets to classify them for use with stateful protocol processing units that can resolve session data spread across multiple data packets and process them for the ultimate destination. The invention replaces a conventional content addressable memory (CAM) with a term addressable memory, whereby redundant terms are recorded with a single memory entry. Two classes of terms are recorded with a single memory entry. Two classes of terms are used to match packet addresses and application ports, as well as a much smaller session CAM that matches the aggregate match of all terms to a specific session. Filed Jan. 8, 2001 . See Lynne Jolitz term memory patent and TCP/IP network accelerator system and method which identifies classes of packet traffic for predictable protocols.
Oracle E-Business Network, Geek of the Week Award (January 2001) for 386bsd (1991-1995) and SiliconTCP (1997-2001) technologies.
US6173333: TCP/IP network accelerator system and method which identifies classes of packet traffic for predictable protocols. Grant Date: Jan. 9, 2001. Jolitz, et al. InterProphet Corporation . A network accelerator for TCP/IP includes programmable logic for performing network protocol processing at network signaling rates. The programmable logic is configured in a parallel-pipelined architecture controlled by state machines and implements processing for predictable patterns of the majority of transmissions. Incoming packets are compared with patterns corresponding to classes of transmissions which are stored in a content addressable memory, and are simultaneously stored in a dual port, dual bank application memory. The patterns are used to determine sessions to which an incoming IP datagram belongs, and data packets stored in the application memory are processed by the programmable logic. Processing of packet headers is performed in parallel and during memory transfers without the necessity of conventional store and forward techniques resulting in a substantial reduction in latency. Packets which constitute exceptions or which have checksum or other errors are processed in software. Filed July 17, 1998 Jolitz et. al. Provisional application filed Jul 18, 1997 (With William F. (Bill) Jolitz). See InterProphet Corporation for product/company/licensing details. See also Term Addressable Memory of an Accelerator System and Method
Patents pending.